This data sheet provides information about the AD9577 clock generator. The AD9577 is a fully integrated dual PLL/VCO core clock generator with 1 integer-N and 1 fractional-N PLL. It supports continuous frequency coverage from 11.2 MHz to 200 MHz and most frequencies from 200 MHz to 637.5 MHz are available.
The AD9577 is a multioutput clock generator optimized for network clocking applications, featuring two on-chip phase-locked loop cores: PLL1 (integer-N) and PLL2 (fractional-N). It supports continuous frequency coverage from 11.2 MHz to 200 MHz and most frequencies up to 637.5 MHz. The device includes integrated loop filters, eliminating the need for external components, and offers up to four LVDS/LVPECL or eight LVCMOS output clocks.
| Frequency Coverage | 11.2 MHz to 200 MHz continuous; up to 637.5 MHz |
|---|---|
| Phase Noise (106.25 MHz LVPECL) | -121 dBc/Hz at 1 kHz |
| Power Dissipation (LVDS) | 1.02 W |
| Power Dissipation (LVPECL) | 1.235 W |
| Operating Voltage | 3.3 V |
| Package | 6 mm x 6 mm, 40-lead LFCSP |
| Operating Temperature | -40°C to +85°C |
The device provides continuous frequency coverage from 11.2 MHz to 200 MHz, with most frequencies available from 200 MHz to 637.5 MHz.
No, the device has integrated loop filters, which conserves valuable design time and board space.
Up to four differential outputs can be configured as LVPECL or LVDS, or up to eight CMOS outputs.