The document describes the requirements for operational amplifiers in sample-and-hold (S/H) circuits, emphasizing the need for low input-bias current, high slew rates, and fast settling times to support 12-bit precision. It highlights that FET-input amplifiers are mandatory to prevent excessive droop rates caused by bias currents.
The text details a specific circuit design using two complementary bipolar (CB) op amps from Analog Devices (AD841 and AD845), three CMOS switches, and passive components. This discrete approach offers a cost-effective alternative to expensive hybrid S/H amplifiers, achieving full-power bandwidths in excess of 250 kHz and acquisition times of approximately 1 µs.
The op amp must have excellent AC performance, low offset voltage and drift, high slew rates, fast settling times, and low input-bias current.
The circuit requires three low-cost CMOS switches, two CB op amps (AD841 and AD845), and a few resistors and capacitors.
The circuit's full-power bandwidth is in excess of 250 kHz.