Fairchild 74HC Logic CMOS SCR Latch-Up Elimination Application Note

About this manual

This document describes the CMOS SCR latch-up phenomenon, a parasitic effect that can cause circuits to malfunction or be destroyed. It details the mechanism involving parasitic P-N-P-N structures within bulk silicon CMOS technologies.

What's inside

• Introduction
• SCR Latch-Up Phenomena
• Simple Discrete SCR Operation
• CMOS SCR Static DC Operation
• Process Enhancements

Frequently asked questions

What is CMOS SCR latch-up?

It is a parasitic phenomenon involving a four-layer thyristor structure (P-N-P-N) that appears from V CC to ground, causing the circuit to malfunction.

How is latch-up triggered in 74HC logic?

It is commonly triggered by applying a voltage greater than V CC or less than ground to any input or output, which forward biases the protection diodes.

How does Fairchild eliminate latch-up?

Fairchild uses proprietary innovations in CMOS processing that reduce transistor betas to eliminate the latch-up mechanism.