This design note explains the effect of clock jitter on high speed ADCs and uses LTC2209 as an example to show how to select a proper clock to mitigate the effect of clock jitter.
Design Note 1013 from Linear Technology provides a technical analysis of how clock jitter impacts the Signal-to-Noise Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) of high-speed Analog-to-Digital Converters (ADCs). The document uses the LTC2209, a 16-bit, 160Msps ADC with an internal aperture jitter of 70 femtoseconds, as a primary case study. It details that while the ADC itself has low intrinsic jitter, external clock sources often introduce significant noise that degrades performance, particularly at higher input frequencies.
The internal aperture jitter of the LTC2209 is 70 femtoseconds.
At 140MHz, the SNR would degrade to 41.1dB.
In HDTV, the sample window is approximately 6400ps.