Analog Devices AD1859 Audio DAC Datasheet

The AD1859 is a complete 16-/18-bit single-chip stereo digital audio playback subsystem. It comprises a variable rate digital interpolation filter, a revolutionary multibit sigma-delta (∑∆) modulator with dither, a jitter-tolerant DAC, switched capacitor and continuous time analog filters, and analog output drive circuitry. Other features include an on-chip stereo attenuator and mute, programmed through an SPI-compatible serial control port. The key differentiating feature of the AD1859 is its asynchronous master clock capability. Previous ∑∆ audio DACs required a high frequency master clock at 256 or 384 times the intended audio sample rate. The generation and management of this high frequency synchronous clock is burdensome to the board level designer. The analog performance of conventional single bit ∑∆ DACs is also dependent on the spectral purity of the sample and master clocks. The AD1859 has a digital Phase Locked Loop (PLL) which allows the master clock to be asynchronous, and which also strongly rejects jitter on the sample clock (left/right clock). The digital PLL allows the AD1859 to be clocked with a single frequency (27 MHz for example) while the sample frequency (as determined from the left/right clock) can vary over a wide range. The digital PLL will lock to the new sample rate in approximately 100 ms. Jitter components 15 Hz above and below the sample frequency are rejected by 6 d


Analog Devices AD1859 Audio DAC Datasheet - cover page
Brand
Analog Devices
Category
Other Electronics
Document type
Datasheet
Language
English
Pages
16
File format
PDF
File size
303 KB
Published
09 May, 2012
Updated
28 September, 2023
MD5 checksum
2A00D9FDDC0D5CCF2DB9FA128B2779E5

About this manual

The AD1859 is a complete 16‑/18‑bit single‑chip stereo digital audio playback subsystem. It integrates a variable‑rate digital interpolation filter, a multibit sigma‑delta modulator with triangular‑PDF dither, jitter‑tolerant DAC, switched‑capacitor and continuous‑time analog reconstruction filters, and buffered outputs with a 64‑step attenuator and mute. The device operates from a single +5 V supply and includes an on‑chip master clock oscillator, requiring only an external crystal.

Key features include continuously variable sample‑rate support, a digital phase‑locked loop that rejects sample‑clock jitter, and optional analog de‑emphasis processing via external passive components. The AD1859 is packaged in 28‑lead SOIC or SSOP and is rated for operation from –40 °C to +105 °C.

What's inside

  • Features
  • Applications
  • Specifications
  • Pin Descriptions
  • Power Supply Connections
  • Analog Performance
  • Digital Timing
  • Definitions
  • Option for Analog De‑emphasis Processing

Specifications

Resolution18 Bits
Dynamic Range94 dB
Supply Voltage+5.0 V
Output Impedance24 Ω
Attenuator Step Size1.0 dB
Power Consumption (both supplies)265‑330 mW

Frequently asked questions

What supply voltage does the AD1859 require?

The AD1859 operates from a single +5 V supply.

What is the dynamic range of the AD1859?

The AD1859 provides a dynamic range of 94 dB.

How many bits of resolution does the AD1859 provide?

It offers 18‑bit resolution.

Does the AD1859 include an on‑chip oscillator?

Yes, it has an on‑chip master clock oscillator; only an external crystal is needed.

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