DS90LV048A 3V LVDS Quad CMOS Differential Line Receiver is a quad CMOS flow-through differential line receiver designed for applications requiring ultra low power dissipation and high data rates.
The DS90LV048A is a quad CMOS flow‑through differential line receiver designed for ultra‑low power dissipation and high data rates up to 400 Mbps (200 MHz). It accepts low‑voltage LVDS inputs (≈350 mV) and provides 3.3 V CMOS outputs with optional tri‑state control and fail‑safe operation for open, shorted, or terminated inputs.
The document includes absolute maximum ratings, electrical characteristics, switching performance, pin descriptions, package options (SOP and TSSOP), and layout recommendations such as power decoupling and differential trace design. Application notes and typical circuit examples illustrate point‑to‑point LVDS connections.
| Maximum data rate | >400 Mbps (200 MHz) |
|---|---|
| Power supply voltage | 3.3 V (+0.3 V tolerance) |
| Static power consumption | 40 mW at 3.3 V |
| Maximum propagation delay | 2.7 ns |
| Channel‑to‑channel skew (typical) | 150 ps |
| Differential skew (typical) | 100 ps |
| Operating temperature range | -40 °C to +85 °C |
| Package types | SOP (M16A) and TSSOP (MTC16) |
The device supports data rates greater than 400 Mbps (200 MHz).
It consumes about 40 mW when powered at 3.3 V.
The output remains in a HIGH state due to internal pull‑up/pull‑down resistors.