The ATT3000 Series Field-Programmable Gate Arrays have high performance, user-programmable, flexible array architecture, standard product availability
This data sheet describes the ATT3000 Series field‑programmable gate arrays, a high‑performance 0.55 µm CMOS FPGA family. It outlines the device architecture, including configurable I/O blocks, a matrix of configurable logic blocks, and programmable interconnect resources.
Key sections cover performance specifications such as toggle rates and LUT delays, detailed I/O options, configuration memory options, package options, and electrical characteristics. The document also lists ordering information and contact details for technical support.
| Maximum toggle rate | 270 MHz |
|---|---|
| LUT delay | <2.7 ns |
| Maximum input transition time | <100 ns |
| Typical hysteresis | ≈300 mV |
| Package options | 44‑Pin PLCC, 68‑Pin PLCC, 84‑Pin PLCC, 100‑Pin QFP, 132‑Pin PPGA, 144‑Pin TQFP, 160‑Pin QFP, 175‑Pin PPGA, 208‑Pin SOFP |
The ATT3000 series can operate at toggle rates up to 270 MHz.
Configuration data can be stored in an external EEPROM, EPROM, or ROM on the board, or loaded from a floppy or hard disk.