The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop.
The HEF4024B is a 7‑stage binary ripple counter with a clock input, asynchronous master reset, and seven fully buffered parallel outputs. The device advances on the high‑to‑low transition of the clock and can be cleared by a high on the master reset.
Typical applications include frequency division and time‑delay circuits. The datasheet lists electrical characteristics such as propagation delays, minimum pulse widths, and maximum clock frequency, as well as package options in both plastic and ceramic DIL formats.
| Number of stages | 7 |
|---|---|
| Package (plastic) | HEF4024BP(N): 14‑lead DIL; plastic (SOT27‑1) |
| Maximum clock frequency | 10 MHz |
| Propagation delay (CP to Op) | 73 ns + (0.55 ns/pF) CL |
It is a 7‑stage binary ripple counter with asynchronous master reset and buffered parallel outputs.
Typical uses are frequency dividers and time‑delay circuits.
The device can operate up to 10 MHz.