S3C44B0X Chinese data manual introduces the features and characteristics of S3C44B0X internal memory controller, including endian, address space, bus width, storage banks, etc
The S3C44B0X microcontroller includes an internal memory controller that provides two sets of necessary memory control signals for external memory operations. It supports up to 8 memory banks with a total address space of 236 MB (32 MB per bank) and programmable bus widths of 8, 16, or 32 bits.
Endianness is selectable via the ENDIAN pin (0 = little‑endian, 1 = big‑endian). Bank configuration registers (BANKCONn) allow setting bus width, wait states, and memory type for each bank. The REFRESH register controls DRAM/SDRAM refresh enable and mode, while the SCLKEN bit can reduce power consumption during SDRAM accesses. This manual is written in Chinese.
| Address space per bank | 32 MB |
|---|---|
| Total address space | 236 MB |
| Number of memory banks | 8 |
| Programmable bus width | 8/16/32 bit |
| Endianness selection pin | ENDIAN |
| Bank0 bus width setting pins | OM[1:0] (00=8‑bit, 01=16‑bit, 10=32‑bit) |
| Number of BANKCONn registers | 8 |
The S3C44B0X has a total of eight memory banks.
Endianness is selected via the ENDIAN pin: 0 for little‑endian and 1 for big‑endian.
Bank0 bus width can be set to 8‑bit, 16‑bit, or 32‑bit using the OM[1:0] pins.