Motorola manuals, page 6
MOTOROLA IBM POWERPC Advance Information PowerPC 604e RISC Microprocessor Technical Summary handbook
This document is a technical overview of the PowerPC 604e microprocessor, a new product developed in collaboration between Motorola and IBM. It describes the features and major functional components of the processor.
MOTOROLA PowerPC 603e RISC Microprocessor Family: PID6-603e (Stretch) Part Number Speci cations handbook
This document describes a new product under development by Motorola, namely the PowerPC 603e microprocessor. It provides information on changes to recommended operating conditions and electrical specifications, as well as listing the differences between this product and the general specifications.
MOTOROLA Advance Information PowerPC 603e RISC Microprocessor Family: PID6-603e Hardware Speci cations handbook(1)
This document contains information on a new product under development by Motorola. It is a product based on the PowerPC 603e RISC microprocessor. The document provides hardware specifications and information on different implementations of the product.
MOTOROLA IBM Advance Information PowerPC 603e RISC Microprocessor Technical Summary handbook
This document provides an overview of a new product developed by Motorola and IBM, introducing the features and characteristics of the PowerPC 603e microprocessor, as well as its compliance with the PowerPC architecture specification.
MOTOROLA Advance Information PowerPC 603e RISC Microprocessor Family: PID6-603e Hardware Speci cations datasheet(1)
MOTOROLA MPC561/MPC562 MPC563/MPC564 RISC MCU Including Peripheral Pin Multiplexing with Flash Code Compression Options handbook
This document provides information about the Motorola MPC561/MPC562 / MPC563/MPC564 RISC MCU, including its high performance CPU system, on-chip watchpoints and breakpoints, program flow tracking, background debug mode, etc.
MOTOROLA MPC555PB/D Rev. 3 2/2003 MPC555 Product Brief handbook
This document introduces the features and characteristics of the MPC555 microcontroller, including the major modular components and major functions.
MOTOROLA MPC5200/D Rev. 2 5/2004 MPC5200 Hardware Specifications handbook
This document is about MPC5200 hardware specifications, mainly introduces the features of MPC5200, including processor core, memory controller, external bus interface and so on.
MOTOROLA MPC2605 Product Preview Integrated Secondary Cache for PowerPC Microprocessors handbook
MPC2605 is a single chip, 256KB integrated look-aside cache with copy-back capability designed for PowerPC applications (MPC603 and MPC604). Using 0.38µm technology along with standard cell logic technology, the MPC2605 integrates data, tag, host interface, and least recently used (LRU) memory with a cache controller to provide a 256KB, 512KB, or 1 MB Level 2 cache with one, two, or four chips on a 64-bit PowerPC bus.
MOTOROLA MPC2105C MPC2106C Manual
The MPC2105C and MPC2106C are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.
MOTOROLA MPC2105A MPC2106A MPC2105B MPC2106B Manual
This is the MPC2105A/B and MPC2106A/B Fast SRAM 512KB and 1MB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms.
MOTOROLA MPC2104P MPC2105P Manual
MOTOROLA FAST SRAM is a 256KB/512KB BurstRAM secondary cache module specifically designed for the PowerPC 60x microprocessor family in compliance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.
MOTOROLA MPC2104 MPC2105 MPC2106 MPC2107 Manual
The MPC2104/5/6/7 are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs. The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used. Bursts can be initiated with the ADS signal. Subsequent burst addresses are generated internal to the BurstRAM by the CNTEN signal. Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control. The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the addr
MOTOROLA MPC2004 MPC2005 Manual
MOTOROLA MPC2002 MPC2003 Manual
MPC2002 and MPC2003 are Motorola's 256KB and 512KB BurstRAM secondary cache modules for PowerPC systems. The modules are configured as 32K x 72 and 64K x 72 bits in a 136-pin dual read single inline memory module (DIMM). The module uses four of Motorola's MCM67M518 or MCM67M618 BiCMOS BurstRAMs. Bursts can be initiated with either transfer start processor (TSP) or transfer start controller (TSC). Subsequent burst addresses are generated internal to the BurstRAM by the burst address advance (BAA) pin. Write cycles are internally self-timed and are initiated by the rising edge of the clock (K) input. Eight write enables are provided for byte write control. The cache family is designed to interface with the PowerPC 60x bus and requires external tag. PD0-PD2 are reserved for density and speed identification.