Integrated Device Technology Manuals

IDT54/74FCT16501AT/CT/ET IDT54/74FCT162501AT/CT/ET IDT54/74FCT162H501AT/CT/ET are 18-bit registered bus transceivers with transparent, latched and clocked modes, produced by Integrated Device Technology, Inc.

This document introduces IDT54/74FCT373T/2373T and IDT54/74FCT573T/2573T, which are high-performance CMOS octal transparent latches with low input and output leakage, CMOS power levels, true TTL input and output compatibility, etc.

This document describes the features and characteristics of the IDT54/74FCT240/244T/AT/CT/DT - 2240/2244T/AT/CT, IDT54/74FCT540/541/2541T/AT/CT FAST CMOS OCTAL BUFFER/LINE DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES product

IDT71V256SA is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. The IDT71V256SA has outstanding low power characteristics while at the same time maintaining very high performance. Address access times of as fast as 10ns are ideal for 3.3V secondary cache in 3.3V desktop designs. When power management logic puts the IDT71V256SA in standby mode, its very low power characteristics contribute to extended battery life. By taking CS HIGH, the SRAM will automatically go to a low power standby mode and will remain in standby as long as CS remains HIGH. Furthermore, under full standby mode (CS at CMOS level, f=0), power consump- tion is guaranteed to always be less than 6.6mW and typically will be much smaller. The IDT71V256SA is packaged in a 28-pin 300 mil SOJ and a 28-pin 300 mil TSOP Type I

The IDT 71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to and remain in, a low-power standby mode as long as CS remains HIGH. In the full standby mode, the low-power device consumes less than 15µW, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5µW when operating off a 2V battery. The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil SOJ, a 28-pin 600 mil DIP, and a 32-pin LCC.

This is a 128k x 8 bit high performance static cmos storage

The IDT6116SA/LA is a 16,384-bit high-speed static RAM organized as 2K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby power mode, as long as CS remains HIGH. This capability provides significant system level power and cooling savings. The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1µW to 4µW operating off a 2V battery. All inputs and outputs of the IDT6116SA/LA are TTL-compatible. Fully static asynchronous circuitry is used, requiring no clock.

IS42S16100C1 is ISSI's 16Mb Synchronous DRAM with 200, 166, 143 MHz frequency. It supports two banks simultaneously and independently, LVTTL interface, 4096 refresh cycles every 64 ms, Random column address every clock cycle, Programmable CAS latency (2, 3 clocks), Burst read/write and burst read/single write operations capability, Burst termination by burst stop and precharge command, Byte controlled by LDQM and UDQM, Industrial temperature up to 143 MHz, 400-mil 50-pin TSOP-II, 60-ball fBGA and Lead-free package option.

The ISSI IS62C1024AL/IS65C1024AL is a low power, 131,072-word by 8-bit CMOS static RAM. It is fabricated using high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques yields higher performance and low power consumption devices. Memory expansion is made easy by using two Chip Enable inputs, CE1 and CE2. Power dissipation can be reduced by using CMOS input levels in standby mode. The features include high-speed access time of 35, 45 ns, low active power of 100 mW (typical), low standby power of 20 µW (typical) CMOS standby, Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications, and fully static operation.

IS61LV6416/IS61LV6416L is a high-performance static RAM chip produced by ISSI company. It has the characteristics of high speed and low power consumption.

This document describes the features and characteristics of the ISSI IS62C256AL/IS65C256AL, a low power 32,768-word by 8-bit CMOS static RAM. It highlights its low power consumption, static operation, and TTL compatible inputs and outputs.

This is a datasheet for IDT74FCT2245AT/CT fast CMOS octal bidirectional transceiver

IS62WV5128ALL/IS62WV5128BLL are high-performance CMOS static RAMs with high speed, low power, three-state outputs, industrial temperature and lead-free.