This document is a user guide for the RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction. It describes the features and characteristics of the product.
Altera Corporation's FPGA series product user manual released in 2012, which introduces the features and behavior of the ALTPLL_RECONFIG megafunction, and how to configure it in the Quartus II software through the parameter editor.
This manual introduces Altera® Embedded Peripherals IP (embedded peripherals IP), which enables you to create, configure, and drive external devices in your system using Altera FPGAs.
This user guide describes the features and behavior of the ALTERA_PLL megafunction that you can configure through the parameter editor in the Quartus® II software.
This datasheet describes the Altera® 10-Gbps Ethernet IP core which implements the IEEE 802.3 2005 and 802.1Q Ethernet standards. The 10-Gbps Ethernet IP core is highly configurable. It includes an Ethernet Media Access Controller (MAC) with an Avalon® Streaming (Avalon-ST) interface on the client side, and a XAUI or a standard XGMII interface on the network side. The XAUI interface is implemented as hard IP in an Altera FPGA transceiver or as soft logic, which results in a soft 10GBASE-X XAUI PCS. Alternatively, you can choose to implement a 10-Gbps Ethernet IP core that includes only the MAC or the soft XAUI PCS.