Philips Manuals (Industrial)

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The 74HC/HCT74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

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74HC/HCT75 Quad bistable transparent latch

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The 74HC/HCT7541 is a high-performance Si-gate CMOS device that is pin compatible with low power Schottky TTL (LSTTL) and is specified in compliance with JEDEC standard no. 7A. It is an octal Schmitt trigger non-inverting buffer/line driver with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high impedance OFF-state. The Schmitt trigger action in the data inputs transforms slowly changing input signals into sharply defined jitter-free output signals.

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74HC/HCT7731 is a high-speed, single-pole, static shift register with recycling mode. Each register has independent data input pins Da to Dd, clock input pins CPa to CPd, and data output pins Qa to Qd. When the clock pulse changes from low to high, the data is shifted one place to the output end. Each recycling mode input controls two registers, RECab controls registers A and B, and RECcd controls registers C and D. When the REC input is high, the device is in the recycling mode and the data at the output end is shifted back to the input end of the register. This makes the data continuously repeated 64 times.

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This data sheet is for 74HC/HCT85 4-bit magnitude comparator

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74HC/HCT86 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT86 provide the EXCLUSIVE−OR function.

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This document describes the features and characteristics of the 74HC/HCT9114 product, including Schmitt trigger action, output capability, logic family specifications, etc.

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This document describes the features and characteristics of the 74HC/HCT93 4-bit binary ripple counter, including various counting modes, asynchronous master reset, etc.

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The 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). The 74HC245; 74HCT245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74HC245; 74HCT245 features an output enable input (OE) for easy cascading and a send/receive input (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

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This document describes the features and characteristics of the 74HC/HCT574 octal D-type flip-flop with positive edge-trigger and 3-state non-inverting outputs for bus oriented applications.

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The 74HC/HCT594 is an 8-bit shift register with output register. Its features are synchronous serial input and output, 8-bit parallel output, shift and storage register have independent direct clear and clocks, 100 MHz (typ.), output capability: – parallel outputs: bus driver – serial outputs: standard, ICC category: MSI, applications: serial-to parallel data conversion, remote control holding register.

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The 74HC/HCT573 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT573 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all latches.

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This document describes the features and characteristics of the 74HC/HCT564 octal D-type flip-flop, including positive-edge triggering, 3-state outputs, and inverting outputs. This product is suitable for bus-oriented applications.

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The document describes the features and characteristics of the 74HC/HCT5555 programmable delay timer with oscillator. It features positive and negative edge triggering, retriggerable or non-retriggerable modes, programmable delay with a minimum of 100ns, and a divide-by range of 2 to 224. The device has a direct reset function to terminate output pulses, Schmitt trigger action on trigger inputs, direct drive for a power transistor, low power consumption, and high precision digital timing. It is suitable for applications such as motor control, delay circuits, automotive applications, etc.

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This document describes an octal buffer/line driver called 74HC/HCT541, which has 3-state outputs. Its features include non-inverting outputs, strong output capability, and belongs to the MSI category.

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This document is a datasheet for 74HC/HCT540, which describes the features and characteristics of the product, including output capability and operating current.

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The 74HC/HCT534 is a high-speed Si-gate CMOS device with 3-state inverting outputs for bus oriented applications. It is an 8-bit positive, edge-triggered register with a common 3-state output enable input, output capability of bus driver and ICC category of MSI.

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The 74HC/HCT4520 is a dual 4-bit synchronous binary counter with standard output capability and MSI ICC category. It is a high-speed Si-gate CMOS device and is pin compatible with the '4520' of the '4000B' series.

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