Guide to creating and configuring a Qsys system with PLL and SDRAM IP cores using Quartus II.
This manual walks you through building your first Qsys system in Quartus II. It covers creating the PLL IP core, configuring its input (50 MHz) and output (100 MHz) clocks, generating the Qsys_system HDL code, and adding the Qsys design to a Quartus project.
The document also explains IO configuration, pin assignment, full compilation, and programming the FPGA with the generated .sof file via a USB‑Blaster. Additional sections describe SDRAM IP core setup (16‑bit, 13 rows, 9 columns, MT48LC16M16A2) and an overview of the EPCS IP core. This manual is written in Chinese.
| PLL input clock frequency | 50 MHz |
|---|---|
| PLL output clock frequency | 100 MHz |
| SDRAM data width | 16 bit |
| SDRAM part number | MT48LC16M16A2 |
| PLL phase offset for SDRAM clock | -63° |
The PLL IP core input clock should be set to 50 MHz.
Connect the USB‑Blaster to the development board, open Quartus II Programmer, ensure the hardware is set up, then program the .sof file.