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- Manuals
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- Languages
- ZH
- Last added
- 2026-09-28
Featured Zircon Opto-Electronic Technology manuals
Zircon Opto-Electronic Technology Qsys_First User Manual
This manual walks you through building your first Qsys system in Quartus II. It covers creating the PLL IP core, configuring its input (50 MHz) and output (100 MHz) clocks, generating the Qsys_system HDL code, and adding the Qsys design to a Quartus project.
The document also explains IO configuration, pin assignment, full compilation, and programming the FPGA with the generated .sof file via a USB‑Blaster. Additional sections describe SDRAM IP core setup (16‑bit, 13 rows, 9 columns, MT48LC16M16A2) and an overview of the EPCS IP core. This manual is written in Chinese.
Covers: Creating PLL IP Core · Configuring Qsys System Code · Adding Qsys to Quartus Project · IO and Pin Assignment · Compiling and Programming FPGA · SDRAM IP Core Configuration
Latest Zircon Opto-Electronic Technology manuals
Zircon Opto-Electronic Technology Qsys_First User Manual
User Manual 92 pages · 5.5 MB · ZHGuide to creating and configuring a Qsys system with PLL and SDRAM IP cores using Quartus II.
Which document do I need?
User Manual
Day-to-day operation, settings and troubleshooting. Start here if the product is already set up.
Questions answered in Zircon Opto-Electronic Technology manuals
What input clock frequency should be set for the PLL IP core?
The PLL IP core input clock should be set to 50 MHz.
From: Zircon Opto-Electronic Technology Qsys_First User Manual
How do you program the FPGA with the generated .sof file?
Connect the USB‑Blaster to the development board, open Quartus II Programmer, ensure the hardware is set up, then program the .sof file.
From: Zircon Opto-Electronic Technology Qsys_First User Manual