The HiSilicon Hi3521DV200 is an H.265 codec AI processor with a quad‑core Cortex‑A7, NNIE inference engine and extensive video interfaces.
The Hi3521DV200 is a system‑on‑chip designed for multi‑channel HD/4K DVR applications. It integrates a quad‑core ARM Cortex‑A7 CPU running at 1.2 GHz, 256 KB L2 cache, NEON/FPU support and a neural network inference engine (NNIE) delivering up to 0.8 Tops of compute for AI tasks such as face detection and object tracking.
The chip provides four MIPI D‑PHY video inputs, HDMI 1.4b, VGA, BT.656/BT.1120, CVBS outputs, as well as SATA, USB, UART, SPI, I2C and Ethernet interfaces. It supports H.265/H.264/JPEG encoding and decoding, multiple bitrate control modes, and includes security engines (AES, RSA, SHA, OTP, secure boot). Typical power consumption is 3.3 W and the package measures 19 mm × 19 mm, operating from 0 °C to 70 °C. This manual is written in Chinese.
| CPU | Quad‑core ARM Cortex‑A7 @ 1.2 GHz |
|---|---|
| L2 Cache | 256 KB |
| Video Codec Support | H.265 Main Profile Level 5.0 encode/decode |
| Maximum HDMI Output | 3840 × 2160 @ 30 fps |
| Package Size | 19 mm × 19 mm |
| Operating Temperature | 0 °C ~ 70 °C |
Through its HDMI 1.4b interface the processor can output up to 3840 × 2160 at 30 fps.