Freescale MCF547x/8x DDR‑SDRAM Layout Considerations Application Note

About this manual

The document describes the DDR‑SDRAM controller integrated in the MCF547x/8x ColdFire microprocessor families and explains how the controller operates at half the core frequency (e.g., 133 MHz for a 266 MHz core). It outlines the memory architecture, supported address widths, chip‑select capabilities, and the maximum memory size that can be accessed.

Detailed layout guidelines are given, including recommended trace lengths, termination resistor values, routing on ground‑adjacent layers, and VREF considerations. Validation board schematics and PCB stack‑up information are provided to illustrate proper implementation.

What's inside

• Introduction
• DDR SDRAM Overview
• DDR SDRAM Controller Implemented on the MCF547x/8x Family
• Layout Guidelines
• Validation Board DDR Layout
• References
• Document Revision History

Specifications

Frequently asked questions

What is the recommended maximum trace length between the MPU and DDR SDRAM?

Trace lengths should be kept less than 6 inches (15 cm) if possible.

How many SDRAM chip selects can the MCF547x/8x controller support?

The controller supports up to four SDRAM chip selects.

What supply voltage is required for current DDR SDRAM devices?

The supply voltage is usually +2.5 V with a +/-5 % tolerance.

Where can the validation board layout files be downloaded?

The files are available on the Freescale ColdFire website at www.freescale.com/coldfire.