The Corebai CBM92AD68 series ADC datasheet provides specifications, features, pin configurations, and performance data for the 125, 105, and 80 variants.
The CBM92AD68 is a dual‑channel, 16‑bit, 125 MSPS analog‑to‑digital converter designed for high‑performance, low‑cost communication applications. It operates from a single 1.8 V supply and offers both 1.8 V CMOS and LVDS output options, with built‑in reference and clock duty‑cycle stabilization.
The document details technical specifications, including power consumption, input bandwidth, SNR, SFDR, pinout, timing diagrams, and packaging information for the QFN‑64 package, as well as application notes for radar, wireless, and ultrasonic systems. This manual is written in Chinese.
| Resolution | 16 bits |
|---|---|
| Sampling Rate | 125 MSPS |
| Supply Voltage (AVDD/DRVDD) | 1.8 V |
| Power Consumption (DC input) | 700 mW |
| Input Bandwidth | 650 MHz |
| Signal‑to‑Noise Ratio (SNR) | 77 dBFS |
| Spurious‑Free Dynamic Range (SFDR) | 85 dBc |
Both AVDD and DRVDD are specified as 1.8 V.
The ADC can sample at up to 125 MSPS.
It supports 1.8 V CMOS or LVDS output levels.
Standby power consumption is 49 mW.