This application note explains how to program parallel EDAC checksum (checkbits) for the FTMCTRL memory controller when using parallel NOR Flash.
The FTMCTRL memory controller is a combined 8/16/32-bit controller that bridges external memory to the on‑chip bus and can protect PROM, SRAM, SDRAM and I/O devices with EDAC. It uses a (39,7) BCH code that generates a 7‑bit checksum for each 32‑bit word.
Programming parallel checkbits requires enabling EDAC, using the write‑bypass (MCFG3.WB) and read‑bypass (MCFG3.RB) fields, and observing strict restrictions such as stopping all DMA, disabling interrupts, and ensuring the programming code resides in cache or on‑chip RAM.
| Data bus width | 8/16/32‑bit |
|---|---|
| Supported device types | PROM, SRAM, SDRAM, I/O |
| EDAC code | (39,7) BCH code |
| Checksum size | 7‑bit per 32‑bit word |
| EDAC enable register | MCFG3 register bit |
A 7‑bit checksum is generated for each 32‑bit word using a (39,7) BCH code that provides single‑error correction and double‑error detection.
Set the EDAC enable bit in the MCFG3 register to activate EDAC protection for the PROM region.
Parallel NOR Flash, MRAM or EEPROM devices are typically used to store the checkbits.