Cobham Gaisler Manuals

Cobham Gaisler FTMCTRL Application Note 32-bit (P)ROM EDAC Checksum Programming

The FTMCTRL memory controller is a combined 8/16/32-bit controller that bridges external memory to the on‑chip bus and can protect PROM, SRAM, SDRAM and I/O devices with EDAC. It uses a (39,7) BCH code that generates a 7‑bit checksum for each 32‑bit word.

Programming parallel checkbits requires enabling EDAC, using the write‑bypass (MCFG3.WB) and read‑bypass (MCFG3.RB) fields, and observing strict restrictions such as stopping all DMA, disabling interrupts, and ensuring the programming code resides in cache or on‑chip RAM.

Covers: Introduction · Overview · FTMCTRL PROM EDAC · Programming parallel checkbits · Controlling the parallel checkbit bus · Device‑specific guidelines