Technical data sheet for the ADAU1781 low‑power 24‑bit stereo audio codec with programmable SigmaDSP core.
The ADAU1781 is a low‑power 24‑bit stereo audio codec that integrates ADC and DAC sections, a 400 mW speaker amplifier, and a programmable SigmaDSP® core. It supports sampling rates from 8 kHz to 96 kHz and offers flexible digital I/O options including I²C, SPI, I²S, left‑aligned, right‑aligned and TDM modes.
The document provides detailed specifications, pin configurations, power‑management modes, clock and PLL settings, as well as performance data for recording and playback paths. It also includes mechanical dimensions, ordering information, and application notes for battery‑powered audio devices.
| Sampling rate range | 8 kHz to 96 kHz |
|---|---|
| Supply voltage (AVDD) | 3.3 V (or 1.8 V option) |
| Dynamic range | −60 dB input |
| Total harmonic distortion + noise | −3 dBFS |
| Typical normal‑mode current consumption | ≈16.84 mA |
| Digital control interfaces | I²C or SPI (configurable for I²S, left/right aligned, TDM) |
It supports sampling rates from 8 kHz up to 96 kHz.
The device supports I²C or SPI control, and the serial audio bus can be configured for I²S, left‑aligned, right‑aligned, or TDM modes.
The analog supply (AVDD) is typically 3.3 V, with an optional 1.8 V configuration.