The 74LVC573A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input precisely or inversely. When the LE is taken low, the Q outputs will be latched precisely or inversely at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while high level the outputs will be in a high impedance state. This device is designed to interface directly High Speed CMOS systems with TTL and NMOS components. It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs are equipped with protection circuits.
The 74LVC573A is a low voltage CMOS octal D-type latch fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is designed for 1.65V to 3.6V operations and features low power consumption and low noise. The device is controlled by a latch enable input (LE) and an output enable input (OE), allowing precise data latching or direct following of input data.
| Operating Voltage Range | 1.65V to 3.6V |
|---|---|
| Propagation Delay (Max) | 6.8ns |
| Output Current (Min) | 24mA |
| ESD Immunity (HBM) | > 2000V |
| Latch-Up Performance | Exceeds 500mA |
| Operating Temperature Range | -55 to 125 °C |
The device operates in a voltage range from 1.65V to 3.6V.
It is an octal device, meaning it has 8 outputs (Q0 to Q7).
The maximum propagation delay is 6.8ns when VCC is 3V.