The document describes a high-speed CMOS single positive edge triggered D-type flip-flop. The flip-flop is fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology and is designed to operate from 4.5V to 5.5V. It features high speed, low power dissipation, compatibility with TTL outputs, and can be used to interface 5V to 3V systems.