This document is about the inquiry of STP1020APGA-50 suppliers. The product has specific features and characteristics.
The document describes the STP1020A as a new member of the SuperSPARC family of microprocessors. It is a highly integrated, high-performance superscalar processor designed using a state-of-the-art BICMOS process. The chip integrates integer and floating-point execution units, a memory management unit (MMU), large level-1 instruction and data caches totaling 36 KBytes, and a bus interface unit supporting two different buses: MBus and VBus.
The STP1020A supports operating frequencies of 50/60 MHz.
The processor includes a total of 36 KBytes of cache memory.
The MBus supports a peak transfer rate of 320 MBytes/s.