This application note describes how to use the STM32F0xx direct memory access (DMA) controller. The STM32F0xx DMA controller, the Cortex™-M0 core, the advanced microcontroller bus architecture (AMBA) bus and the memory system contribute to provide a high data bandwidth and to develop very-low latency response time software. This application note also describes how to take full advantage of these features and ensure correct response times for different peripherals and subsystems.
This document details the features and usage of the Direct Memory Access (DMA) controller found in STM32F0xx microcontrollers. It explains how the DMA controller facilitates high-speed data transfers between peripherals and memory, as well as between memory blocks, without CPU intervention. The note covers the DMA overview, data management strategies, and interrupt handling mechanisms.
| Number of DMA channels | 5 |
|---|---|
| Maximum data transfer count | 65536 |
| Priority levels | 4 levels |
The DMA controller provides high-speed data transfer between peripherals and memory as well as memory to memory without any CPU actions.
Priorities are software programmable with four levels (very high, high, medium, low) or hardware-based if priorities are equal.
Interrupts are generated for Half Transfer, Transfer Complete, and Transfer Error events.