This application note describes the EMI asynchronous mode configuration for interfacing to standard memory devices in Section 1: Interfacing with asynchronous memory. It covers also EMI Synchronous mode which has a different bus timing and configuration in Section 2: Interfacing with synchronous memory.
This document describes the STR91xFA External Memory Interface (EMI) bus, which is a flexible, user-programmable bus capable of interfacing with various memory types including SRAM, Flash, ROM, and PSRAM. The note details programmable features such as multiplexed or non-multiplexed bus modes, bus width selection, and timing configurations.
The guide is divided into two main sections: interfacing with asynchronous memory and interfacing with synchronous memory. It provides specific configurations for read and write bus cycles, address latch signals, and chip select assignments, along with circuit examples for connecting to 16-bit Flash and SRAM devices.
| Supported Memory Types | SRAM, Flash memory, ROM or PSRAM |
|---|---|
| Bus Width Options | 8 or 16 bit |
| Address Lines Select | AO-15 or AO-A23 |
| Bus Access Modes | Asynchronous or synchronous |
| Chip Select Signals | CSO-3 |
The bus can interface with SRAM, Flash memory, ROM, or PSRAM.
The bus width can be configured for 8 or 16 bit operations.
Yes, the bus supports both asynchronous and synchronous bus access.