STMicroelectronics SPEAr1310 Datasheet

This data brief provides a detailed overview of the features and capabilities of the STMicroelectronics SPEAr1310 dual-core Cortex A9 embedded MPU for communications, including the CPU subsystem, bus, memories, connectivity, and other features.


STMicroelectronics SPEAr1310 Datasheet - cover page
Brand
STMicroelectronics
Category
microcontrollers
Document type
Datasheet
Language
English
Pages
57
File format
PDF
File size
806 KB
Published
06 August, 2012
Updated
30 September, 2023
MD5 checksum
F98586180132EE7187EA724EFF61A57F

About this manual

The SPEAr1310 is a dual-core Cortex-A9 embedded multi-purpose unit (MPU) designed for cost and power-sensitive networking applications. It is manufactured using STMicroelectronics' 55nm HCMOS low power silicon process and supports both symmetric and asymmetric multiprocessing.

What's inside

  • Description
  • Multilayer interconnect matrix
  • Cortex-A9 subsystem
  • Clock and reset system
  • Power control module
  • BootROM
  • Static RAM
  • Multiport memory controller
  • Giga/Fast Ethernet
  • PCI Express

Specifications

CPU Cores2x ARM Cortex-A9
CPU Frequencyup to 600 MHz
L1 Cache932+32 KB per core
L2 Cache512 KB
Process Technology55nm HCMOS
Ethernet Ports2x Giga/Fast Ethernet
PCIe Links3x PCIe 2.0
SATA Ports3x SATA gen-2
USB Port1x USB2.0 OTG
UARTs6x UARTs
I2C Ports2x I2C ports

Frequently asked questions

What is the maximum CPU frequency of the SPEAr1310?

The SPEAr1310 features Cortex-A9 cores with a frequency of up to 600 MHz.

What silicon process is used for the SPEAr1310?

The device is manufactured with STMicroelectronics' 55nm HCMOS low power silicon process.

Does the SPEAr1310 support symmetric multiprocessing?

Yes, it supports both symmetric (SMP) and asymmetric (AMP) multiprocessing.

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