This document describes the features and characteristics of the SPC560P50L3, SPC560P50L5, SPC560P44L3, and SPC560P44L5, which are 32-bit Power Architecture™ based MCU products. It includes a single-issue, 32-bit CPU core complex, variable length encoding (VLE), on-chip flash memory with ECC, on-chip RAM with ECC, fail-safe protection, Nexus L2+ interface, interrupt controller, general purpose I/O, timers, and communication interfaces.
The document describes the features of the SPC560Px family, a series of next-generation automotive microcontrollers based on the Power Architecture Book E architecture. These devices are specifically designed for embedded applications in chassis systems, such as Electrical Hydraulic Power Steering (EHPS) and lower-end Electrical Power Steering (EPS), as well as airbag applications.
Key features include a single-issue 32-bit CPU core complex compliant with Power Architecture embedded category, up to 512 KB of on-chip flash memory with ECC, and various fail-safe protection mechanisms like a programmable watchdog timer. The microcontroller integrates multiple communication interfaces including FlexCAN, LINFlex, DSPI, and FlexRay, along with two 10-bit analog-to-digital converters (ADC) and enhanced timers.
| CPU Core | Single issue, 32-bit CPU core complex (e200z0h) |
|---|---|
| Flash Memory | Up to 512 KB on-chip flash memory with ECC |
| RAM | Up to 40 KB on-chip RAM with ECC |
| ADC Channels | Two 10-bit analog-to-digital converters (2x 13 input channels) |
| FlexCAN Interface | 1 FlexCAN interface (2.0B Active) with 32 message objects |
| FlexRay Module | 1 FlexRay module (V2.1) with dual or single channel, up to 10 Mbit/s |
| LIN Channels | 2 LINFlex channels (LIN 2.1) |
Yes, it includes a programmable watchdog timer, junction temperature sensor, non-maskable interrupt, and fault collection unit.
The document notes a revision replacing an erroneous 60 MHz core speed with 64 MHz.