This application note describes how the M24LR64-R Multi-Bank reference design works from the schematics and design perspective, and explains how to configure and use it
The document describes the M24LR64-R multi-bank reference design, which allows users to increase memory density by connecting several M24LR64-R devices in parallel on the same I2C bus and sharing a single antenna. STMicroelectronics provides two specific reference designs: ANT4-M24LR-A (2-bank, 128-Kbit) and ANT5-M24LR-A (4-bank, 256-Kbit).
| Operating Frequency | 13.56 MHz |
|---|---|
| Standard Compliance | ISO/IEC 15693 |
| Memory Capacity (Single Device) | 64-Kbit |
| Memory Capacity (4-Bank Design) | 256-Kbit |
| Max Devices per Bus | 4 |
It helps users increase the memory density of their Dual Interface EEPROM by connecting several devices in parallel.
Up to four devices can be accessed by using the EO and E1 bits of the Device Select code.
The equivalent tuning capacitance is 4 times that of a single M24LR64-R device.