This document details analysis and implementation of a reliable bus topology for 8 clustered TigerSHARCs (ADSP-TS101S) plus a host processor and external SDRAM.
This application note describes the analysis and physical implementation of a reliable bus topology for a system consisting of 8 clustered ADSP-TS101S TigerSHARC processors, a host processor, and external SDRAM. The primary goal is to achieve reliable communication at a performance target of 100 MHz. The document investigates various system topologies and concludes that a star pattern topology is the only solution that meets this stringent performance requirement.
| Performance Target | 100 MHz |
|---|---|
| Cluster Size | 8 devices |
| Topology Type | Star pattern |
| Simulation Frequency | 50 and 100 MHz |
| Termination Resistance | 50 Ohms |
| Termination Capacitance | 330pF |
| Max Trace Length L1 | 3.0 inches |
| Max Trace Length L2 | 2.0 inches |
| Max Trace Length L3 | 1.0 inches |
A star pattern topology is recommended as it is the only configuration that meets the 100 MHz performance goal.
The system uses AC termination with a resistor matching the transmission line impedance (50 Ohms) and a capacitor of 330pF.
The maximum transmission line lengths are 3.0 inches for L1, 2.0 inches for L2, and 1.0 inch for L3.