The AD800/AD802 is Analog Devices' second generation clock recovery and data retiming phase-locked loop, supporting data rates of 20-160 Mbps.
The AD800 and AD802 employ a second-order phase-locked loop architecture to perform clock recovery and data retiming on Non-Return to Zero (NRZ) data. These devices support standard telecommunications bit rates, including DS-3, STS-1, and STM-1, without requiring an external VCXO or preamble for lock acquisition.
The document provides comprehensive technical specifications covering operating conditions, performance parameters such as jitter tolerance and static phase error, pin descriptions, thermal characteristics, and typical application circuits. It includes specific data for various models like the AD800-45BQ, AD800-52BR, and AD802-155KR/BR.
| Nominal Center Frequency (AD800-45) | 44.736 MHz |
|---|---|
| Supply Voltage | +5 V or –5.2 V |
| Jitter Peaking (Damping Factor 5) | 0.08 dB |
No, these devices do not require a preamble or an external VCXO to lock onto input data.
The device acquires lock on random or scrambled data within 4 × 10^5 bit periods when using a damping factor of 5.
The jitter tolerance is 0.47 Unit Intervals at a frequency of 30 kHz.