UT1553B RTI Remote Terminal Interface Datasheet

This document describes the features and characteristics of RTI-1, including full compliance with MIL-STD-1553B Remote Terminal interface, support for dual-redundant data bus operation, internal illegal command definition capability, automatic DMA control and address generation, etc.


UT1553B RTI Remote Terminal Interface Datasheet - cover page
Brand
UT1553B
Category
Other device
Document type
Datasheet
Language
English
Pages
52
File format
PDF
File size
1023 KB
Published
06 June, 2012
Updated
29 September, 2023
MD5 checksum
69915D137A80380E146251B85301ECB0

About this manual

The UT1553B RTI is an interface device designed to link a MIL-STD-1553 serial data bus with a host microprocessor system. It features complete compliance with the MIL-STD-1553B standard, including support for dual-redundant data bus operation and internal illegalization of selected mode codes.

The device includes encoding/decoding logic, error detection, command recognition, memory address control, clock, and reset circuits. It is available in ceramic 84-lead leadless chip carrier and 84-pin pingrid array packages with a full military operating temperature range from -55°C to +125°C.

What's inside

  • Architecture and Operation
  • Host Interface
  • Internal Register Description
  • Mode Codes and Subaddresses
  • Memory Map Example
  • Pin Identification and Description
  • Maximum and Recommended Operating Conditions
  • DC Electrical Characteristics
  • AC Electrical Characteristics
  • Package Outline Drawings

Specifications

Input Clock Frequency12MHz
Output Clock Frequency2MHz
Built-in Timer Duration730ms
Memory Space Size2K x 16

Frequently asked questions

Does the device support dual-redundant data bus operation?

Yes, it supports dual-redundant data bus operation.

What is the function of the built-in timer?

The built-in 730ms timer is activated when the encoder is about to transmit and is reset upon receipt of a valid command or time-out.

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