The document describes the features and characteristics of RTI-1, including full compliance with MIL-STD-1553B Remote Terminal interface, support for dual-redundant data bus operation, internal illegalization of selected mode code commands, external illegal command definition capability, etc.
The UT1553B RTI is an interface device designed to link a MIL-STD-1553 serial data bus with a host microprocessor system. It features complete compliance with MIL-STD-1553B requirements, including ASD/ENASC testing and support for dual-redundant data bus operation.
The document details the architecture, internal registers, and electrical characteristics of the device. Key operational features include automatic DMA control, address generation, and a built-in 730ms timer activated during transmission. The RTI is available in ceramic 84-lead leadless chip carrier and 84-pin pin grid array packages.
| Input Clock Frequency | 12MHz |
|---|---|
| Output Clock Frequency | 2MHz |
| Built-in Timer Duration | 730ms |
| Memory Space Size | 2K x 16 |
Yes, it supports dual-redundant data bus operation.
JAN-qualified devices are available for this interface.