LINEAR Maximize the Performance of 16-Bit 105Msps ADC with Careful IF Signal Chain Design Design Note 468 Clarence Mayott Derek Redmayne

This document describes how to optimize the performance of a 16-bit, 105Msps ADC by carefully designing the intermediate frequency (IF) signal chain to maximize overall system performance. The article provides detailed information on the signal chain topology and design considerations for each stage. Finally, the LTC2274 ADC is recommended as an excellent choice with excellent AC performance and high dynamic range.

Brand: Linear Technology
Category: Other Electronics
Document type: Application Note
Language: English
Pages: 2
File format: PDF
File size: 91 KB
Published: 05 June, 2012
Updated: 29 September, 2023
Model: LTC2274
MD5 checksum: 6C3B2AE78664A9F1B75924931803233A
PDF: LINEAR Maximize the Performance of 16-Bit 105Msps ADC with Careful IF Signal Chain Design Design Note 468 Clarence Mayott Derek Redmayne PDF

About this manual

This application note describes how to optimize an analog front end for the LTC2274, a 16-bit, 105Msps ADC. It details a specific signal chain topology optimized for a 70MHz center frequency and 20MHz bandwidth, utilizing components like the AH31 amplifier and SAW filters.

What's inside

Introduction
Signal Chain Topology
First Stage Amplification
SAW Filter Selection
Second Stage Amplification
Output Stage Requirements
Conclusion

Frequently asked questions

What are the stated resolution and sample rate of the LTC2274?

The device is a 16-bit, 105Msps ADC.

What are the stated SNR and spurious free dynamic range ratings?

It has 77dB of SNR and 100dB of spurious free dynamic range.

What is the insertion loss of the SAW filter used in the signal chain?

The insertion loss of the SAW filter is about -15dB.

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