UTRON UT62L1024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits.
The UT62L1024 SRAM provides 128 K×8‑bit storage with three‑state outputs, fully static operation and TTL‑compatible I/O. It is designed for low‑power battery‑backed applications and operates from a single 2.7 V to 3.6 V supply.
Key features include multiple package options (PDIP, SOP, TSOP‑1, STSOP), standby currents as low as 0.5 µA, and guaranteed data retention down to 2 V. Detailed electrical characteristics, timing diagrams, and absolute maximum ratings are provided for design integration.
| Access time | 35/55/70 ns (max) |
|---|---|
| Operating current | 40/35/30 mA typical |
| Standby current | 2.5 µA (L‑version) / 0.5 µA (LL‑version) typical |
| Supply voltage range | 2.7 V to 3.6 V |
| Package options | 32‑pin 600 mil PDIP, 32‑pin 450 mil SOP, 32‑pin 8×20 mm TSOP‑1, 32‑pin 8×13.4 mm STSOP |
| Input high voltage | 2.0 V minimum |
| Input low voltage | -0.5 V to 0.6 V |
| Data retention voltage | 2 V minimum |
The access time is 35 ns, 55 ns, or 70 ns (maximum) depending on the operating condition.
It operates from a single supply voltage between 2.7 V and 3.6 V.
Typical standby current is 2.5 µA for the L‑version and 0.5 µA for the LL‑version.
The device is offered in 32‑pin 600 mil PDIP, 32‑pin 450 mil SOP, 32‑pin 8×20 mm TSOP‑1, and 32‑pin 8×13.4 mm STSOP packages.