The AD6641 is a 250 MHz bandwidth DPD observation receiver with high signal-to-noise ratio, excellent linearity, and integrated features. It uses a 12-bit parallel CMOS and 6-bit DDR LVDS interface, and supports high-speed synchronization capability. The product has low power dissipation and programmable input voltage range, among other features.
The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12‑bit 500 MSPS ADC, a 16 k × 12 FIFO, and multiple output interfaces (12‑bit parallel CMOS, 6‑bit DDR‑LVDS, SPI, SPORT). It provides high dynamic performance, low power consumption, and on‑chip reference and sample‑and‑hold functions, making it suitable for broadband communications, test equipment, and power‑amplifier linearization.
Key specifications include 65.8 dBFS SNR at 500 MSPS, 10.5‑bit ENOB, 695 mW power dissipation at full rate, programmable input range of 1.18 V–1.6 V, and a maximum output data rate of 62.5 MHz. The device operates from a single 1.9 V supply, is offered in a 56‑lead LFCSP package, and meets industrial temperature range (‑40 °C to +85 °C).
| Resolution | 12 bits |
|---|---|
| Signal‑to‑Noise Ratio (SNR) | 65.8 dBFS at 500 MSPS |
| Power Dissipation | 695 mW at 500 MSPS |
| Programmable Input Voltage Range | 1.18 V to 1.6 V |
The device consumes 695 mW when operating at 500 MSPS.
Both analog and digital supplies are 1.9 V (AVDD = 1.9 V, DRVDD = 1.9 V).
The AD6641 is offered in a 56‑lead lead‑frame chip‑scale package (LFCSP) and a tape‑and‑reel version of the same package.