RM7000B is a 64-bit MIPS RISC microprocessor with integrated L2 Cache from PMC-Sierra. It has a dual-issue symmetric superscalar microprocessor, a maximum CPU frequency of 500MHz, and the ability to issue two instructions per clock cycle. It also has integrated primary and secondary caches, a high-performance system interface, and other features.
The RM7000B is a 64‑bit MIPS RISC microprocessor featuring a dual‑issue symmetric superscalar core, up to 500 MHz CPU frequency, and integrated primary (16 KB instruction, 16 KB data) and secondary (256 KB L2) caches. It offers a 1000 MB/s peak system interface, a high‑performance floating‑point unit delivering up to 1000 MFLOPS, and a rich set of interrupt and DSP‑oriented instructions.
The device is supplied in a 304‑pin TBGA package (31 × 31 mm) fabricated in a fully static 0.13 µm CMOS process. Development tools include Linux (MontaVista, Red Hat), VxWorks, Nucleus, QNX Neutrino, and compiler suites from Green Hills and others. Typical applications span voice gateways, DSLAMs, routers, set‑top boxes, and cellular base stations.
| Maximum CPU frequency | 500 MHz |
|---|---|
| L2 cache size | 256 KB |
| Instruction cache size | 16 KB |
| Data cache size | 16 KB |
| System bus frequency | 125 MHz |
| Peak throughput | 1000 MB/s |
| Floating‑point performance | 1000 MFLOPS |
| Package type | 304‑pin TBGA, 31 × 31 mm |
| Process technology | 0.13 µm CMOS |
The RM7000B can run at up to 500 MHz.
It includes a 256 KB on‑chip secondary (L2) cache.
Supported OSes include Linux (MontaVista, Red Hat), VxWorks, Nucleus, and QNX Neutrino.
The processor is offered in a 304‑pin TBGA package measuring 31 × 31 mm.