Motorola manuals, page 21
MOTOROLA MC74AC132/MC74ACT132 handbook
MC74AC132/74ACT132 Four-input NAND Schmitt Trigger
MOTOROLA MC74AC126/MC74ACT126 handbook
MC74AC126 and MC74ACT126 are Quad Buffer with 3-State Outputs, support TTL compatible inputs and 3-state enable input, the maximum operating voltage is 7V, the maximum input current is 20mA, the maximum output current is 50mA.
MOTOROLA MC74AC125/MC74ACT125 handbook
This document describes the features and characteristics of the MC74AC125 and MC74ACT125 products. They are quad buffers with TTL compatible inputs and outputs, featuring high voltage level, low voltage level, and high impedance outputs. The document also provides maximum ratings and recommended operating conditions.
MOTOROLA MC74AC113/MC74ACT113 handbook
MC74AC113/74ACT113 is a high-speed independent triggered JK dual D flip-flop
MOTOROLA MC74AC112/MC74ACT112 handbook
The MC74AC112/74ACT112 consists of two high-speed completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH • Outputs Source/Sink 24 mA • ′ACT112 Has TTL Compatible Inputs CP VCC CP1 K1 J1 SD1 Q1 Q1 CD1 CD2 CP2 K2 J2 SD2 CD J Q Q2 SD CONNECTION DIAGRAM Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K Q CP SD K Q CD J Q MODE SELECT — TRUTH TABLE Operating Mode Inputs Outputs Operating Mode SD CD J K Q Q Set L H X X H L Reset (Clear) H L X X L H *Undetermined L L X X H H Toggle H H h h q q Load “0” (Reset) H H l h L H Load “1” (Set) H H h l H L Hold H H l l q q H, h = HIGH Voltage Level L, l = LOW Voltage Level X = Don’t Care l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the HIGH to LOW clock transition. *Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously.
MOTOROLA MC74AC11/MC74ACT11 handbook
This is a document about MC74AC11 and MC74ACT11 products. These products are triple 3-input AND gates with TTL compatible inputs and high output sink/source current capabilities. They operate at a voltage range of 2.0V to 6.0V and have fast input rise/fall times.
MOTOROLA MC74AC10/MC74ACT10 handbook
MC74AC10/MC74ACT10 is a triple 3-input Nand gate in the MC74 series. It has a high output voltage, and its input voltage range is -0.5 to VCC +0.5 V. The input current is ±20 mA and the output current is ±50 mA.
MOTOROLA MC74AC109/MC74ACT109 handbook
MC74AC109/74ACT109 are two high-speed, completely independent transition clocked JK flip-flops
MOTOROLA MC74AC08/MC74ACT08 handbook
MC74AC08 and MC74ACT08 are quad 2-input AND logic gates with output drive capability of 24 mA. MC74ACT08 has TTL compatible inputs.
MOTOROLA MC74AC05/MC74ACT05 handbook
The MC74AC/ACT05 is a device that is pin-compatible with the LS05. The device inputs are compatible with standard CMOS outputs and, with pull-up resistors, they are compatible with TTL outputs. The outputs can source/sink 24 mA, and the ′ACT05 has TTL-compatible inputs.
MOTOROLA MC74AC04/MC74ACT04 handbook
MOTOROLA MC74AC02/MC74ACT02 handbook
MC74AC02/MC74ACT02 is a digital logic device of the MC74 series, belonging to a quad 2-input NOR gate, with an output current of up to 24mA, and can be compatible with TTL circuits
MOTOROLA MC74AC00/MC74ACT00 handbook
This document describes the characteristics of MC74AC00 and MC74ACT00, two quad 2-input NAND gates. They have TTL compatible inputs and can output a current of 24mA. The maximum ratings include VCC from -0.5V to +7V, input/output voltage from -0.5V to VCC+0.5V, maximum input current of ±20mA, and maximum output sink/source current of ±50mA.
MOTOROLA MC100LVE210/MC100E210 handbook
MOTOROLA MC10E196/MC100E196 handbook(1)
The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications. The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control. The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195. An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.