ANALOG Manuals

This document is the user guide for the evaluation board of AD company's ADF4001 integer-N PLL frequency synthesizer. It describes the features and functions of the evaluation board, as well as the accompanying software and additional equipment required.

This document is the user guide for the evaluation board of the ADF4153 fractional-N PLL frequency synthesizer. The evaluation board includes the synthesizer, VCO, TCXO for reference frequency, and loop filter. The accompanying software allows complete control of synthesizer functions from a PC. It is designed for 25 MHz PFD frequency, 2.5 mA charge pump current, and 50 kHz loop bandwidth.

This document is a user guide for the GSM900 evaluation board for a PLL frequency synthesizer. The evaluation board is a self-contained board that includes the synthesizer, VCO, and loop filter for generating GSM frequencies. It is designed for a 20 kHz loop bandwidth and allows complete control of synthesizer functions from a PC using accompanying software. The board can be operated with either a 3V or 5V power supply and has typical phase noise performance of -91 dBc/Hz at 1 kHz offset and better than -90 dBc spurious performance at 200 kHz offset from the carrier.

The ADF4002-EP frequency synthesizer is a 400MHz bandwidth frequency synthesizer that supports 2.7V to 3.3V power supply, uses a 3-wire serial interface, and can implement clock conditioning, clock generation and IF LO generation.

This document is the product manual of Analog Devices ADF4106-EP frequency synthesizer

This document is the user guide for the evaluation board of the 7.5 GHz PLL frequency synthesizer. It provides detailed information about the on-board power supplies, OP27, and the connection to an external VCO board.

The AD9547 Rev. B dual/quad input network clock generator/synchronizer is a highly integrated clock generator capable of generating a single or dual differential output clock from any input reference frequency from 1 kHz to 750 MHz. The device supports automatic/manual holdover and reference switching, and provides up to 450 MHz of output clock frequency.

This application note describes the features of the ADV601JS12, ADV601LC and ADV611 and ADV612 video codecs and differences from the original ADV601.

This engineer’s note covers crystal requirements for clocking Analog Devices’ AC97 codecs.

This document introduces the features and usage of the SSM2167 evaluation board, provides the connection and power supply instructions for the evaluation board, and provides the PCB schematics and layout of the evaluation board.

This document introduces the functions and usage of the 10-bit display interface board, including application scenarios, usage restrictions, package contents, and usage requirements.

The AD9985 incorporates an auto-offset function. The Auto-Offset works by monitoring the output of each ADC during the clamp period and then calculating the required offset setting to yield a given output code. When auto- offset is enabled (Reg. 0x1D:7 = 1), the settings in the target code registers (0x19 to 0x1B) are used by the auto-offset circuitry as desired clamp codes. The circuit compares the output code during clamp to the target code and adjusts the offset up or down to compensate. In auto-offset mode, the target code is an 8-bit, twos complement word, with Bit 7 of their respective registers being the sign bit.

This document describes how to send compressed digital video from one ADV601LC-based Video-pipe evaluation board to another Video-pipe board. This enhancement of the Video-pipe board function is accomplished merely by replacing the standard Video-pipe firmware with special firmware. No hardware modifications are necessary. The firmware to transmit video is dubbed TRANLAYR. The firmware to receive is called RECVLAYR. TRANLAYR and RECVLAYR communicate video using the ISO 13818 (otherwise known as H.222.0) transportation protocol over the 8 Megabit/sec serial ports of the Video-pipe boards. The TRANLAYR program accepts standard analog video from a TV camera or other source and outputs compressed digital video. The RECVLAYR program is the inverse, it accepts compressed digital video and outputs standard analog video to a TV monitor. This Applications note is for hardware and software designers starting an ADV601 design. Using this note and the information in any ADV601 family Video Codec data sheet you can do the following: Use Video-pipe boards as engineering mock-ups on compressed video projects. Understand how to select compressed video bit rates. Understand the theory of operation of TRANLAYR and RECVLAYR. Know how to program EPROMs and assemble the...