ANALOG Manuals

AD604 Rev. G is a dual-channel ultralow noise variable gain amplifier with extremely low input noise and programmable gain range. It is suitable for applications such as ultrasound and sonar time-gain controls, high-performance AGC systems, and signal measurement.

AD605 Rev. F is a dual, low noise, single-supply variable gain amplifier. It features 2 independent linear-in-dB channels, with input noise at maximum gain of 1.8 nV/√Hz, 2.7 pA/√Hz, and a bandwidth of 40 MHz (-3 dB). It has a programmable absolute gain range, with a gain range of -14 dB to +34 dB (FBK shorted to OUT) or 0 dB to 48 dB (FBK open). It also has variable gain scaling, stable gain with temperature and supply variations, single-ended unipolar gain control, and other features.

The AD603 is a low noise, voltage controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin selectable gains of −11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to 51+ dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is 1.3 nV/√Hz, and gain accuracy is ±0.5 dB.

AD600/AD602 are dual-channel, low noise, wideband variable gain amplifiers with linear dB gain response and 2 gain ranges. They feature accurate absolute gain, low input noise, low distortion, high bandwidth, and stable group delay. These products are suitable for ultrasound imaging systems, high-performance audio and RF AGC systems, signal measurement, and other applications.

ADV601 is a low-cost multi-format video codec that features precise compressed bit rate control, field-independent compression, flexible video interface, supports all common formats including CCIR-656, general purpose 8-, 16- or 32-bit host interface with 512 deep 32-bit FIFO.

The ADV202 is a single-chip JPEG2000 video codec with patented SURF® (spatial ultra-efficient recursive filtering) technology, enabling low power and low cost wavelet-based compression.

The ADV7202 is a video sampling codec with features including four 10-bit video DACs, 10-bit video rate digitization, AGC control, and multi-channel inputs.

The AD1893 SamplePort is a fully digital, stereo Asynchronous Sample Rate Converter (ASRC) that solves sample rate interfacing and compatibility problems. It features low cost, low power consumption, automatic sensing of sample frequencies, rejection of sample clock jitter, accommodation of dynamically changing asynchronous sample clocks, a wide range of sample clock frequencies, and performance with 96 dB THD+N.

The AD1896 is a 24-bit high performance single-chip second generation asynchronous sample rate converter

The AD1895 is a 24-bit, high performance, single-chip, second generation asynchronous sample rate converter. It offers features such as a THD + N range of -115 dB to -122 dB (depending on sample rate and input frequency), 128 dB (A-Weighted) dynamic range, 192 kHz sampling frequencies, improved jitter rejection, and 1:8 upsampling and 7.75:1 downsampling ratios.

The AD7652 is a 16-bit, 500 kSPS, charge redistribution SAR analog-to-digital converter that operates from a single 5 V power supply

The AD7684 is a 16-bit, 100 kSPS differential ADC from Analog Devices. It features 16-bit resolution, 100 kSPS throughput, ±1 LSB typical full-scale linearity, ±3 LSB maximum full-scale linearity, ±VREF differential input range, 2.7 V to 5.5 V single-supply operation, SPI-®/QSPI-™/MICROWIRE-™/DSP-compatible serial interface, 4 mW @ 5 V, 1.5 mW @ 2.7 V, 150 µW @ 2.7 V/10 kSPS power consumption, 1 nA standby current, and an 8-lead MSOP package. The AD7684 is primarily used in battery-powered equipment, data acquisition, instrumentation, medical instruments, and process control applications.

AD667 is a complete 12-bit D/A converter, featuring a dual-buffered latch and single-chip high stability buried Zener reference. The converter uses 12 precision high speed bipolar current steering switches and a laser trimmed thin-film resistor network to provide fast settling time and high accuracy. Microprocessor compatibility is achieved by the on-chip dual-buffered latch. The design of the input latch allows low input current and ensures linear dependence of output offset voltage on input bias current.