Shuming SLM2304S Gate Driver Application Manual

This manual describes the functions, peripheral circuit design, parameter selection and layout guidelines for the SLM2304S HVIC gate driver used to drive up…


Shuming SLM2304S Gate Driver Application Manual - cover page
Brand
Shuming
Category
Other Electronics
Document type
Application Note
Language
Chinese
Pages
10
File format
PDF
File size
1.4 MB
Published
30 September, 2026
Updated
30 September, 2026
MD5 checksum
32D130D9B85E2AA5AF93430A584D708B

About this manual

The SLM2304S HVIC gate driver from Shuming is designed for high‑voltage applications such as BLDC motors, high‑power DC‑DC converters, household appliances, stepper drivers and inverters. It integrates UVLO protection, interlock control and a bootstrap supply to ensure safe operation of high‑side MOSFETs/IGBTs.

Key design topics covered include UVLO threshold settings, interlock behavior, bootstrap capacitor and resistor selection, gate‑resistor calculation, and PCB layout recommendations to minimise parasitic inductance and EMI. Practical circuit examples and design equations are provided to help engineers implement reliable high‑side driver solutions. This manual is written in Chinese.

What's inside

  • Introduction
  • UVLO (Under‑Voltage Lockout) Function
  • Interlock Function
  • Typical Application Circuits
  • Bootstrap Capacitor Design
  • Gate‑Resistor Selection
  • Layout and PCB Recommendations
  • Component Selection Guidelines

Specifications

Maximum drive voltage600 V
UVLO hysteresis voltage0.7 V
Typical VDD supply voltage12–15 V
Internal pull‑down resistance on HIN/LIN≈500 kΩ
Recommended bootstrap resistor value5–10 Ω
Recommended gate‑resistor (RGATE) calculationRG = 1/(CISS·2π·fR·Q)

Frequently asked questions

What does the UVLO function do?

UVLO shuts off the driver output when VCC/VBS falls below the low‑threshold (VCCUV‑/VBSUV) and re‑enables it only after the voltage rises above the high‑threshold (VCCUV+/VBSUV).

What is the purpose of the interlock function?

The interlock ensures that when both high‑side and low‑side inputs are high, both outputs are forced low to prevent shoot‑through of the MOSFET/IGBT pair.

What are the recommended input decoupling components?

Use a combination of an electrolytic capacitor (10–100 µF) and a 100 nF ceramic capacitor close to the VDD and COM pins.

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