SEGGER J-Link ARM JTAG Emulator Rev 3.0 User Manual

About this manual

The SEGGER J-Link Rev 3.0 is an ARM JTAG emulator supporting ARM7, ARM9 and Cortex‑M3 cores. It connects via USB, provides high‑speed download (up to 800 kB/s with DCC) and includes features such as automatic speed detection, voltage monitoring, and a TCP/IP server.

The manual explains driver installation, configuration for major IDEs (IAR, KEIL, ADS, WINARM, RealView), J‑FLASH ARM usage, and includes appendices on GDBserver, command‑line flashing, and the new V6 hardware with SWD support. This manual is written in Chinese.

What's inside

• J-Link ARM JTAG Emulator Introduction
• J‑LINK Driver Installation
• J‑LINK Settings in Development Environments
• J‑FLASH ARM Usage Settings
• FAQ
• Appendix A: Using J‑LINK GDBserver
• Appendix B: J‑Flash ARM Command Line
• Appendix C: V6 Version Features and SWD Usage

Specifications

Frequently asked questions

What is the maximum JTAG clock speed of the J‑Link?

The J‑Link supports a maximum JTAG speed of 12 MHz.

Which ARM cores are supported by the J‑Link?

It supports all ARM7/ARM9 cores and Cortex‑M3, including ARM7TDMI, ARM7TDMI‑S, ARM720T, ARM920T, ARM926EJ‑S, ARM946E‑S, ARM966E‑S.

Does the V6 version support SWD debugging?

Yes, only the V6 version of J‑Link supports the SWD interface for Cortex‑M3 devices.