Intel D400 and D500 Series Processor Datasheet

This Intel Atom D400/D500 Series processor datasheet provides specifications, signal descriptions, functional and electrical details.


Intel D400 and D500 Series Processor Datasheet - cover page
Brand
Intel
Document type
Datasheet
Language
English
Pages
79
File format
PDF
File size
603 KB
Published
03 October, 2026
Updated
03 October, 2026
MD5 checksum
5EC43B6E4F258C33E99F50B480EDBA55

About this manual

The datasheet covers the Intel® Atom™ D400 and D500 Series processors, describing their architecture, integrated memory controller, GPU, and I/O features. It includes detailed signal descriptions, functional operation, power management, and thermal specifications for system designers.

Key sections provide electrical ratings, voltage identification (VID) requirements, package mechanical drawings, and debug tool specifications, helping engineers design compliant motherboards and platforms.

What's inside

  • Introduction
  • Signal Description
  • Functional Description
  • Electrical Specifications
  • Signal Quality Specifications
  • Low Power Features
  • Thermal Specifications and Design Considerations
  • Package Mechanical Specifications and Ball Information
  • Debug Tool Specifications
  • Testability

Specifications

Instruction cache size32 KB
Data cache size24 KB
L2 cache configuration2 × 512 KB 8‑way for D510 dual‑core, 1 × 512 KB 8‑way for D410 single‑core
Maximum memory capacity4 GB (DDR2 or DDR3)
DMI interface lanes4 lanes, 2.5 Gbps per lane
VID pins7 voltage identification pins (VID[6:0])
Supported power‑management statesC0 and C1 only

Frequently asked questions

What is the maximum memory capacity supported by the D400/D500 series?

The processors support up to 4 GB of DDR2 or DDR3 memory.

How many DMI lanes does the processor provide?

It provides four DMI lanes, each capable of 2.5 Gbps.

What are the core cache sizes of the D400/D500 processors?

Each core has a 32 KB instruction cache, a 24 KB data cache, and L2 cache up to 512 KB per core.

Which power‑management states are supported?

Only the C0 and C1 power‑management states are supported.

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