This manual provides schematic design guidelines for Gowinsemi GW1NS, GW1NSR, GW1NSE, and GW1NSER series FPGAs, covering power, JTAG, MSPI, clocks, and…
This document serves as a schematic design guide for the Gowinsemi GW1NS, GW1NSR, GW1NSE, and GW1NSER series of FPGA products. It details specific device characteristics and special usage rules required for circuit board design.
The guide covers essential topics including power supply requirements for different versions (LX, UX, LV), JTAG and MSPI configuration interfaces, clock pin definitions, differential signaling standards, and configuration control signals such as RECONFIG_N, READY, and DONE. This manual is written in Chinese.
| Core Voltage (VCC) | 1.14V to 1.26V |
|---|---|
| UX Version VCCX Min | 2.375V |
| Power Rise Slope | 0.6mV/μs ~6mV/μs |
| RECONFIG_N Pulse Width | 25ns |
It acts as a reset function for FPGA programming configuration; pulling it low prevents any configuration operations.
It indicates that the FPGA configuration has been successfully completed.
The configuration mode is selected via the MODE0, MODE1, and MODE2 signals.