The General Vision CM1K hardware user manual explains the chip architecture, neural network operation, optional features and hardware design guidelines.
This manual describes the CM1K pattern‑recognition chip, a 1024‑neuron parallel silicon neural network with optional recognition stage and I²C slave controller. It covers the architecture, bus structure, timing constraints and programming sequences needed to integrate the chip into a system.
Additional sections provide hardware design options, mechanical and electrical specifications, power‑saving tips, and a FAQ that addresses common implementation questions.
| Pin count | 100 pins (TQFP) |
|---|---|
| Die size | 8 mm × 8 mm |
| Maximum operating clock frequency | 27 MHz (single‑chip configuration) |
| Power consumption (idle) | 15 mW |
| Power consumption (active) | ~275 mW |
| Operating temperature range | 0 °C to 70 °C |
| Interface levels | LVTTL |
The chip runs up to 27 MHz in a single‑chip configuration (S_CHIP=1).
The CM1K contains a network of 1024 neurons.
The RECO_EN, VI_EN and I2C_EN pins should be grounded if their functions are not used.
The die measures 8 mm × 8 mm.