The C‑SKY CK802 CPU User Manual details the processor's features, architecture, programming model, instruction set, registers, pipeline, exception handling…
The CK802 is a low‑cost, ultra‑low‑power 32‑bit embedded CPU core developed by C‑SKY Microsystems. It targets smart‑card, smart‑grid, low‑cost micro‑controller and wireless sensor network applications and implements a mixed 16/32‑bit RISC instruction set.
The manual covers the processor's micro‑architecture, programming model, data formats, full register set, 32‑bit and 16‑bit instruction encodings, pipeline operation, exception handling, work‑mode switching, and provides appendices with MPU configuration examples and an instruction glossary. This manual is written in Chinese.
| Maximum operating frequency | 50 MHz (worst case) |
|---|---|
| Dynamic power consumption | < 80 µW/MHz |
| Performance | 0.95 DMIPS/MHz |
| Configurable cache sizes | 2 KB, 4 KB, 8 KB |
| Interrupt sources supported | 1, 2, 4, 8, 16, 24, or 32 sources |
The CK802 can run up to 50 MHz in the worst‑case scenario.
Its dynamic power consumption is less than 80 µW per MHz.
The processor supports configurable cache sizes of 2 KB, 4 KB, or 8 KB.
It can handle 1, 2, 4, 8, 16, 24, or 32 interrupt sources.