LA76931S is a new dual-chip (CPU + decoder) color TV dedicated super chip developed by Japanese Sanyo Company. Our company has developed corresponding control software and masked the dual-chip super chip, which can be used in 14 inches to 29 inches of the machine core, and has a variety of functional extensions, can be realized in a single PCB main board from simple to high-grade full series of machine core.
This manual describes the hardware features of the LA76931S TV decoder chip, including RAM, ROM, CPU timing, ports, AD converters, and interrupt sources. It also details the software functions such as channel scanning, EEPROM handling, and language options.
The document includes full pin‑out diagrams, port control tables, factory‑logo settings, and procedures for automatic debugging and EEPROM programming, aimed at technicians who need to service or program the device. This manual is written in Chinese.
| RAM | 512 x 8 bits |
|---|---|
| ROM | 32K or 48K selectable |
| CPU instruction cycle | 0.85 ns |
| TO ports | 10 input/output definable ports |
| AD converters | 5 × 8‑bit |
| PVW output ports | 3 × 7‑bit |
| Timer/Counter | 16‑bit |
| Interrupt sources | 15 sources, 9 entries |
| Crystal frequency | 32.768 kHz |
It has five 8‑bit AD converters.
The CPU minimum instruction cycle is 0.85 ns.
The chip provides 15 interrupt sources with 9 interrupt entries.
A 32.768 kHz crystal is used.