zero-riscy: User Manual

This manual describes the design of ZERO-RISCY, a 32-bit RISC architecture that can be used in the design of ASICs and FPGAs.

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PDF
Published
19 October, 2023
Updated
19 October, 2023
MD5 checksum
6FDC67C729B2834387DF8278C4044B67
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zero-riscy: User Manual PDF
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