This document describes a chip with high speed, low power consumption, TTL compatible inputs, and bidirectional parallel communication capabilities.
The 74LVC161284 is a high-speed, low-power bidirectional transceiver designed for IEEE 1284 Extended Capabilities Port (ECP) mode communication between personal computers and printing peripherals. It contains eight high-speed non-inverting bidirectional buffers and eleven control/status non-inverting buffers with open-drain outputs, fabricated in silicon gate C2MOS technology.
The device supports both IEEE 1284-I (Level 1) and IEEE 1284-II (Level 2) standards. It features a High Drive (HD) input that enables the cable port to switch from open-drain to a high-drive totem-pole output, capable of sourcing 14mA on all buffers and 84mA on the peripheral logic output. The Direction (DIR) input controls the data flow direction between the A and B ports.
| Propagation Delay (Max) | 9ns |
|---|---|
| Quiescent Supply Current (Max) | 20µA |
| Operating Voltage Range | 3.0V to 3.6V |
| High Level Input Voltage (Min) | 2V |
| Low Level Input Voltage (Max) | 0.8V |
| A Port Output Drive | 4mA Totem Pole |
| B Port Drive Capability | 14mA |
| Peripheral Logic Output Drive | 84mA |
| Package Type | TSSOP |
It supports IEEE STD 1284-I (Level 1 Type) and IEEE STD 1284-II (Level 2 Type) for bidirectional parallel communications.
No, pull-up resistors are integrated on all open-drain outputs, eliminating the need for discrete resistors.
DIR (Active HIGH) enables data flow from A port to B port, while DIR (Active LOW) enables data flow from B port to A port.