The 74LCX573 is a low voltage CMOS octal D-type latch with 3-state non-inverting output fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and high speed 3.3V applications; it can be interfaced to 5V signal environment for both inputs and outputs. These 8 bit D-Type latch are controlled by a latch enable input (LE) and an output enable input (OE). While the LE inputs is held at a high level, the Q outputs will follow the data input. When the LE is taken low, the Q outputs will be latched at the logic level of D input data. While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (OE) is in high level, the outputs will be in a high impedance state. It has same speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption. All inputs and outputs are equipped with protection circuits against static discharge.
The 74LCX573 is a low voltage CMOS octal D-type latch with 3-state outputs, fabricated with sub-micron silicon gate technology. It is designed for low power and high-speed 3.3V applications while maintaining compatibility with 5V signal environments for both inputs and outputs. The device features power-down protection on inputs and outputs, symmetrical output impedance, and balanced propagation delays.
| Operating Voltage Range | 2.0V to 3.6V |
|---|---|
| Data Retention Voltage | 1.5V |
| Max Propagation Delay | 8.0 ns |
| Latch-Up Performance | > 500mA |
| ESD Performance (HBM) | > 2000V |
| Operating Temperature | -55 to 125 °C |
Yes, it has 5V tolerant inputs and outputs, allowing it to be interfaced to 5V signal environments.
The maximum propagation delay is 8.0 ns at a supply voltage of 3V.
The device is available in SOP and TSSOP packages.